1. Field of the Invention
The present invention relates to a packet switch for use in a packet switching system or the like which switches packetized information and, more particularly, to a large capacity packet switch which permits the accommodation of a number of high-speed trunks in the packet switching system.
2. Description of the Prior Art
Conventionally known as a packet switch is a bus matrix switch, which has such an arrangement as shown in FIG. 1.
In FIG. 1 input packets transmitted over trunks 101 to 10n are subjected to predetermined processing in received packet processing equipment 301 to 30n, by which the received packets are each added with a packet header specifying any one of transmitted packet processing equipment 311 to 31n, thereafter being provided on that one of column buses 201 through 20n which is connected to the specified transmitted packet processing equipment. At intersections of the column buses 201 to 20n with row buses 211 to 21n there are provided cross point elements (XE) 411 to 4nn. The cross point element 4ij acquires only the packet whose header has a destination j, that is, the packet destined for the transmitted packet processing equipment 31j, and the acquired packet is temporarily stored in a buffer 400 depicted in FIG. 2.
Having stored the packet in the buffer 400, the cross point element 4ij sends to the row bus 21j a use-of-bus request for transmission of the packet. The request is detected and controlled by one of bus control circuits 32l to 32n for each row bus and access permission is given to only one cross point element 4ij, after which the packet is sent out.
FIG. 2 illustrates the arrangement of the cross point element 4ij. The headers of the packets received from the column bus 20i are checked for their destination by a control circuit 40l and only those destined for the row bus 21j are loaded into the buffer 400. The buffer 400 is what is called a FIFO (First-In First-Out) memory which outputs data in the order of input. The row bus 21j includes a data bus 21j-1 which transmits packets and a control bus 21j-2 which transmits control signals for request and permission.
According to the prior art described above, however, a bus matrix switch with n inputs and n outputs calls for n.sup.2 cross point elements. On this account, the prior art is disadvantageous economically in that an increase in the number n will cause a marked increase in the number of cross point elements needed.